1. Field
The present disclosure relates generally to processing systems employing a bus architecture, and more specifically, to methods and apparatuses for performing an atomic semaphore operation.
2. Background
Computers have revolutionized the electronics industry by enabling sophisticated processing tasks to be performed with just a few strokes of a keypad. These sophisticated tasks involve an incredibly high number of complex components that communicate with one another in a fast and efficient manner using a bus. A bus is a channel or path between components in a computer.
Many buses resident in a computer have traditionally been implemented as shared buses. A shared bus provides a means for any number of components to communicate over a common path or channel. In recent years, shared bus technology has been replaced to a large extent by point-to-point switching connections. Point-to-point switching connections provide a direct connection between two components on the bus while they are communicating with each other. Multiple direct links may be used to allow several components to communicate at the same time. A bus arbiter may be used to manage communications over the bus.
Conventional bus design includes independent and separate read, write, and address channels. A component granted access to the bus by the bus arbiter may perform a read or write operation by placing an address on the address channel and sending the appropriate read/write control signal using sideband signaling. When the component writes data to another component on the bus, it sends the data over the write channel. When the component reads data from another component on the bus, it receives the data over the read channel.
A computer implementing a bus architecture may include a number of processing components connected to memory. The memory may be divided into regions either by the system designer or dynamically during operation. Each processing component may have its own dedicated memory region. “Shared memory regions,” on the other hand, are memory regions that may be accessed by multiple processing. A semaphore may be used to manage access to the shared memory regions. A “semaphore” is a hardware or software flag, residing in a shared memory location, that indicates the accessibility of a shared resource. A processing component that needs access to the shared memory region may read the semaphore to determine the accessibility of the shared memory region. If the semaphore indicates that the shared memory region is available, then the processing component may set the semaphore to indicate that the shared memory region is locked, and proceed to access the memory. The process of reading and setting the semaphore needs to be performed atomically. That is, no other processing component should be able to access the semaphore during this process.
Atomic access to the semaphore is not inherent with conventional bus protocols. Instead, it is a special case that is added to the bus protocol and often requires special hardware. The additional hardware increases the complexity of the bus arbiter and the processing components, and may result in added processing delay within the system. Accordingly, there is a need in the art to implement atomic access to the semaphore within the framework of the bus protocol with minimal additional hardware without degrading performance.